MDVE realtime testbed
MDVE testbeds are setups for hardware-in-the-loop (HITL) testing of S/C functions or components - e.g. for AOCS closed loop tests or tests of the onboard computers. The testbed setup consists of the hardware to be tested, the front-end equipment to be connect to it, a system simulator for simulation of the rest of the S/C and the control system (core EGSE).An emulation of the new generation on-board processor (ERC32) for an integrated software verification facility (SVF) is under development. The realtime testbed is one configuration of the Astriums "Model based Development & Verification Environment " (MDVE).
Features / technical details
- Simulator
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- real-time S/C simulator based on special configurable STP/UML/C++ design
- target platforms Sun (Solaris) and Motorola-68xx/PowerPC/VME (VxWorks)
- Front-End Equipment
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- standard VME board set for analog, digital, serial, thermistor, ... interfaces (to be tailored to
- individual project interface requirements)
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- standard VME board set for TM/TC interfaces
- Man-Machine Interface
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- test-bed control via core EGSEØ
- simulator MMI
Categories
Applications
- Satellite AIV (Phase C/D)
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- HITL subsystem testing
- Onboard S/W verification with HITL (e.g. OBC breadboard in the loop)
- S/W Maintenance Facility (Phase E)
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- onboard S/W verification for OBSW upgrades during S/C operationsØ
- onboard S/W patch verification for problem fixing during S/C operations
Reference customers
ESTEC Project: SSVF Phase 1 & 2
Grace: Grace System Testbed
CryoSat: CryoSat Breadboard Integration Tests (end 2001)
